Parity Prediction for Partitioned Incremental Registers
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
A technique is described whereby parity prediction is used to detect errors in the operation of incrementable registers, for use in computer systems. The concept is used where incrementable registers must be partitioned as part of the logical functions implemented and checked for errors. Different functional portions of a register are brought together in the error detection sense, resulting in parity prediction which is similar to a single register. The three portions of the instruction address registers (IARs), as shown in the figure, are partitioned registers used to hold the real address of an instruction. Instructions may either be fetched from main storage thirty-two bits at a time or from a read only storage (ROS) unit eight bits at a time.