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Circuit for Detecting Failure of Clock Oscillator

IP.com Disclosure Number: IPCOM000040395D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Belliveau, MJ Schlak, RB Visentin, TJ [+details]

Abstract

The drawing shows a logic circuit for detecting the failure of circuits that produce a signal X(t) on a line 2. In a simple example, the signal X(t) has a symmetrical rectangular waveform that is up for the first half of each period and down for the second half. This waveform is passed along a chain of delay circuits 3, 4 and 5 in which each delays the waveform for half the period. The outputs of these circuits are successive half periods of the waveform designated X(t-D), X(t-2D) and X(t-3D). If the clock is operating properly, no more than two consecutive signals will be both up or both down at any time. A logic circuit 6 receives these signals and produces an output that signifies that the signal X(t) is stuck at a down level.