Browse Prior Art Database

Parallel Processing of Systems Network Architecture Finite State Machines

IP.com Disclosure Number: IPCOM000040398D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Loucks, L Thompson, E Vicknair, WE Wierwille, B [+details]

Abstract

Architectural specifications for Systems Network Architecture (SNA) fail to exploit the inherant parallelism of the set of finite state machines (FSMs) used in SNA. The described method comprises software that identifies global states and inputs, and processes them in parallel in order to increase performance of a SNA implementation. A SNA basic information unit (BIU) is made up of a request/-response header (RH) and a request unit (RU). In the course of its processing, a BIU has its RH checked to determine if it is in violation of some SNA protocol. The Half Session component of SNA enforces several protocols (e.g., chaining, request/response mode, send/receive mode, and bracket protocols). Each of these protocols is enforced by a FSM procedure.