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N+ Guard Rings for CMOS Technology

IP.com Disclosure Number: IPCOM000040405D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Barber, JR Kotecha, HN Stanasolovich, D [+details]

Abstract

This article discloses a process for forming self-aligned guard rings during n-well formation to minimize latch-up of CMOS devices. Step 1 - Thermal silicon oxide 10 is grown on substrate 12 (Fig. 1). A layer of photoresist 14 is applied on oxide 10, and the n-well pattern is lithographically defined (Fig. 2). Step 2 - The pattern in the photoresist layer 14 has been transferred to the oxide 10 with an anisotropic dry etch with a high oxide/silicon etch rate ratio. After the pattern has been delineated in the oxide layer, a high energy ion implant creates the n-well region 16 (Fig. 3). Step 3 - The photoresist is stripped and a conformal CVD (chemical vapor deposition) nitride film is deposited. The nitride film is then blanket etched in order to form nitride spacers 18 on the sidewalls of the oxide 10 (Fig. 4).