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Direct Loads and Stores for a Binary Floating Point Unit Disclosure Number: IPCOM000040428D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

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Rodriguez, JR [+details]


This article describes a technique that provides for automatic format conversion at the execution of direct loads and stores from and to main storage in a reduced instruction set computer (RISC)-type architecture. The technique used includes the necessary means to perform automatic format conversions as is required in a binary floating point (FP) bus unit architecture supporting direct load and store instructions. The drawing illustrates the system organization for RISC architecture in block diagram form. The basic architecture defines a computational instruction set of reduced complexity. This allows the processing unit (PU) implementation to be hardwired, and by using organizational techniques, such as pipelining, instructions can complete execution in one machine cycle.