Browse Prior Art Database

Microprocessor-Controller Communication Technique

IP.com Disclosure Number: IPCOM000040446D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Andrews, CL Felix, RA [+details]

Abstract

Parallel bus communication between a central microprocessor and subordinate microprocessors can accommodate interrupt-driven controllers of different types and provide full checking of all transmitted data. The communication link is a star configuration with the central controlling processor, or main engine, as the nucleus, and any number of subordinate processors, also referred to as controllers, forming the arms of the star. (Image Omitted) The main engine, such as an Intel 80186, uses half-duplex communication via an eight-bit parallel bus with several printer mechanism controllers, such as carriage, ribbon, print and stacker mechanisms. The controllers may be Intel 8051 microprocessors with the communication interface I/O mapped to the main engine.