The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Request/Grant Interface for Personal Computers

IP.com Disclosure Number: IPCOM000040471D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue


Related People

Lo, YC Moeller, DL Tran, LT [+details]


A technique is described whereby personal computers (PCs), which contain three address bus masters on a local address bus, are provided with control circuitry so as to ensure the required priority occurrence of memory refresh cycles. A straightforward implementation is to route an interrupt signal from central processing unit (CPU) gate array 10, as shown in the figure, to processor 11. There would be no communication between gate array 10 and co-processor 12. Problems are known to occur in this approach in that in some operations co-processor 12 requires control of the address bus for a set period of time. Consequently, during a refresh operation, the refresh controller in CPU gate array 10, which is a higher priority device than co-processor 12, may be 'shut out' of bus control by the co-processor.