Direct Memory Access Write Delay Circuitry for Personal Computers
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
A technique is described whereby a delay circuit is implemented within the direct memory access (DMA) circuitry of a personal computer (PC) so as to prevent marginal timing interference when long data access features are used. With the advent of faster memory devices, which require fast access to information on a data or address bus, the concept described herein provides a wait state, incorporated into memory circuitry, to compensate for the timing requirements of the memory devices. For example, slow devices such as diskette memory read circuitry is considerably slower, as compared to fast memory devices which require valid data sooner; therefore, a delay in the start of a memory write cycle is needed.