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Buffer Management and Switching Mechanism for Cached DASD Control Unit

IP.com Disclosure Number: IPCOM000040494D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Brady, JT [+details]

Abstract

A method is described for managing a DASD cache buffer, comprising the steps of (a) formatting cache data into a plurality of chained blocks, each block comprising control information and data, and (b) interleaving the transfer of control information of each block with the transfer of data of a previous block. Fig. 1 is an example of a data block format of the present invention. In addition to the data, each block has a forward pointer for chaining the next block. Optionally, a block may also have control information, such as the number of bytes to be accessed in the buffer (buffer count), and a verification pattern which is used upon initial reference of a block to verify that the block is correct. Fig. 2 illustrates the logic of a cache interface for interleaving the transfer of block control information and data.