Display Architecture for Rapid Character Update
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
In an all-points-addressable (APA) display, each bit of a bit buffer memory corresponds to a pixel of the display. An architecture is provided in which memory words in the bit buffer memory are addressed (or mapped) in a vertical arrangement. In addition to the vertical addressing feature, the present invention includes write masking, logical functions, and barrel shifting. Write masking defines which bits in the bit buffer memory can (and cannot) be written over. The vertical arrangement permits the display to use existing microprocessor functions which facilitate the rapid movement of memory words (or blocks of memory words) in memory.