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Static Memory Write Address Decoder With Blanket Write Capability Using Single Phase Positive Active System and Test Clocks and Cmos Pass

IP.com Disclosure Number: IPCOM000040499D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Correale, A Szydlowski, CP [+details]

Abstract

Transfer gates and simple primitive logic are configured to provide a circuit which performs a write address decoder, having the capability of writing all memory bits simultaneously for tests, and using single phase positive active system and test clocks. Fig. 1 illustrates the circuit realization used to implement the write decoder, which requires the complement of the system clock. A complement clock signal C2 is generated from the positive system clock C2 and provided as an input to the chip. The C2 signal gates a four to sixteen decoder which includes an additional input, a positive active test clock PCLK capable of overriding the write address decode, to write all bits simultaneously. The primary decoder is a six-input NOR current 10: four address inputs, the complemented C2 clock C2, and PCLK.