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Scannable Latch Circuitry to Interface With Combinational Logic Designs

IP.com Disclosure Number: IPCOM000040515D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Hsu, Y Mraz, R Tsao, M [+details]

Abstract

A technique is described whereby a scannable latch circuit provides the interface capability to various combinational logic circuitry, so as to enable prototype circuit designs to be implemented for early examination. The prototype circuits, which are not easily simulated, therefore provide the ability to examine timing paths and clocking signals at the early stages of a system design. The concept centers around the use of L1/L2 latch circuitry, typically found in gate array logic provided by many vendors. The scannable latch circuit chip is designed so as to interface with all +5 volt transistor-transistor logic (TTL) technology, including CMOS and FAST. It contains eight single-bit scan latches in one twenty-four pin DIP (dual inline package) and facilitates wirewrap capabilities.