Low Power Word Line Driver
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Proposed is a circuit improvement in a word line driver for gated arrays with Harper-type cells which drastically reduce the power consumption, without impairing the performance. Some types of fast bipolar memory cells, such as Harper-type and CTS (Complementary Transistor Switch) cells, comprise two word lines. The driver and decoder circuits for those cells are very complex and marked by high power dissipation to reach the required performance. The figure shows an improved word line driver with a decoder. Word line decoder TD1 ... TD4 is controlled by input signals A1 and A2 and is activated by clock signal CL (down level). Node OP is pulled up, turning transistor T11 on. Then the charge stored in the saturated PNP transistor T14 (PNP current mirror) and on charge supply line CSL is discharged by transistor T13.