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Improvement in Bipolar RAM Biasing

IP.com Disclosure Number: IPCOM000040530D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Lawson, WF Walach, AZ [+details]

Abstract

A typical random-access memory (RAM) cell is shown in Fig. 1 with its bias interconnection shown in Fig. 2. Total bias current, I, is distributed through on-chip wiring represented by resistors r1 and r2 (Fig. 2). Microamperage level in any individual cell is a function of r1 and r2, which are layout dependent, and of base-emitter voltage (VBE) tracking of cell transistors T1 and T2 with the VBEs of other array cells. Variations in cell biasing result in proportional variations in cell offset, WV, and these in turn affect the array's performance and reliability. If transistor T3 is included inside the cell of Fig. 1, the bias distribution problem is moved to EE-bus, which does not enhance bias sharing on the EE-bus. An improvement, which is described in the following, requires an addition of cell resistor R3 (Fig.