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Improved Vector Operations in Store-In Cache Machines

IP.com Disclosure Number: IPCOM000040539D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Emma, PG Knight, JW McAuliffe, K Pomerene, JH Rechtschaffen, RM Sparacio, FJ [+details]

Abstract

This invention provides improved cache performance in machines with store-in caches that use large vector operands. This performance advantage is obtained by performing specific vector storage operations directly to memory, that is, by storing "around" rather than "in" the cache. The cache represents a performance sensitive area for processors with a vector processing capability. When such processors derive their operand activity from a store-in cache, an improvement can be realized for a subset of Vector Register Store (VRS) operations. When the VRS operations represent an update to the entire line in memory, several efficiencies can be realized.