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Recessed Lateral Double-Heterojunction Bipolar Junction Transistor

IP.com Disclosure Number: IPCOM000040546D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Harder, C Van Zeghbroeck, BJ [+details]

Abstract

Proposed is a lateral double-heterojunction bipoplar junction transistor structure designed for GaAs technology.The device is compact, allowing high package density, and has low parasitic capacitances. With base widths of below 1 nm, it provides for high speed performance. The fabrication of the transistor is simple; it does not require ion-implantation or subsequent annealing. The device is schematically shown in the figure. It can be fabricated as outlined below: - On a semi-insulating GaAs (SI GaAs) substrate, the following layers are subsequently grown using Molecular Beam Epitaxy (MBE): p+ GaInAs (100 nm thick; doping level: 1019 cm-3), n Al GaAs (50 nm; 1018 cm-3), n+ GaInAs (50 nm; 1019 cm-3The latter layer serves to provide good ohmic contacts.