Browse Prior Art Database

FIFO Register for Graphics Display

IP.com Disclosure Number: IPCOM000040552D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Taylor, JL [+details]

Abstract

This disclosure is a modification of the arrangement shown in the IBM Technical Disclosure Bulletin 29, 3164-3165 (December 1986), to make the FIFO (first-in, first-out) more general purpose and to provide a fast LSSD bit-sliced FIFO of arbitrary width and depth which will accept and supply data at irregular intervals. The disclosure relates to any system where data must be queued between processes, e.g., a display where page mode bursts of data are queued for serialization or where data to be written to memory must be queued so that bursts of write cycles may be interleaved with refresh reads. The basic bit-slice for the design is shown in Fig. 1. The bit- slice contributes two layers to the depth of the FIFO and comprises control logic and FIFO data-holding registers.