Browse Prior Art Database

High Performance Multi-Chip Module

IP.com Disclosure Number: IPCOM000040557D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Olson, LT [+details]

Abstract

A multi-chip ceramic module design enhances the wirability and electrical performance capability of metallized ceramic polyimide (MCP) chip carriers. The module is constructed and works as described below. A single-chip MCP module has two levels of metal, a bottom layer M1 and a top layer M2 (Fig. 1A). The module has pins which are flush, or flush with a chamfer, on the top surface module. The M1 metal is used for power plane(s), and the M2 level contains all signal conductors. Fig. 1B depicts a ceramic substrate containing two levels of metal M3 and M4. Signal lines are placed on M3, and power plane(s) on M4. A square hole, which is slightly larger than the chip (Fig. 1A), is located at the center of the substrate. A matrix of pads which access M3 or M4 planes by vias are also shown on the top surface.