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Algorithm for 3-Bit Overlapped Scanning Multiplication

IP.com Disclosure Number: IPCOM000040561D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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Grab, AV Stein, AW Vassiliadis, SN [+details]


Significant reductions in processing time and cost result from using two or more parallel chips for multiplying with the 3-bit overlapped scanning technique. The chips can be common part numbers and use concurrent decoding and addition with a minimal-width adder. Assuming a floating point 56-bit multiplier x and 56-bit multiplicand y with bit O as most significant and bit 55 as least significant, multiplier x is divided into bits (0-27) and (28-55) and multiplied with y for each circuit chip to provide respective high and low partial products of PPRH and PPRL. These partial products (Fig. 1) are each of 84 bits that are added after displacement of PPRL to the right 28 bit positions to give a result of 112 bits. Only the over (Image Omitted) lapping parts RB and RC need to be added, as shown in Fig. 2.