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CMOS Output Inverter Circuit With Low-Power Test Output Inverter

IP.com Disclosure Number: IPCOM000040584D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Takada, S [+details]

Abstract

This article describes a CMOS output inverter circuit provided with a low-power test output inverter. The test output inverter is provided in parallel with the output drive inverter and used only to produce test outputs in test mode. The CMOS output drive inverter, which consists of series-connected P-type and N-type field-effect transistors (FETs) is usually comprised of very large transistors to provide a sufficient driving ability. When operated at a high frequency for testing, such an inverter can cause a large transient current through both the FETs, increasing power consumption and generating noise signals. To prevent this, a low-power CMOS test output inverter made up of small transistors is added as a test output stage. Fig.