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Array Test System Word Line/Data Output Redundancy Circuit

IP.com Disclosure Number: IPCOM000040596D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Anemojanis, E Schuster, JM [+details]

Abstract

Disclosed is a circuit that determines if failing data outputs and word lines can be replaced by redundant circuits on an array chip under test. Referring to the figure, a part number program (PNP) loads a data output (DO) limit register 10 and the redundant (RDN) word line (WL) counter 12 with the number of redundant circuits on the array. Any failures detected during a test sequence load a product DO register 14 with a bit that identifies the failing DO. The DO fail bit is transferred to a corresponding WL temporary latch 16, one latch for each array DO. The outputs of the latches 16 are coupled to a random- to-binary (R/B) converter read-only memory (ROM) 18. The R/B ROM 18 is preprogrammed to convert the number of active inputs to a corresponding binary number.