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Self-Aligned Diffusion Contact Process

IP.com Disclosure Number: IPCOM000040598D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Barber, J Stanasolovich, D [+details]

Abstract

A process for making self-aligned contacts to diffusion or polysilicon regions of an FET is described. This process can be used with standard processes which allow borderless contacts for increased circuit density. Referring to Fig. 1, a substrate 10 is shown having a polysilicon gate 12 overlying a thin gate oxide 14. Diffusion regions 16 and 18 have been ion implanted. Oxide spacers 20 and 22 have been defined, along with oxide cap 24 over the polysilicon 12. A conformal coating of titanium is deposited on the structure with a thickness equal to the desired width of the diffusion contacts. The titanium coating is then reactive ion etched using BCl3 followed by Cl2 . The resulting titanium spacers 26 and 28 are shown in Fig. 2. (Image Omitted) Next, a thin layer of oxide is deposited followed by a layer of photoresist.