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Self-Aligned Process for Forming Polysilicon Contacts Over ROX or Gate Oxide Disclosure Number: IPCOM000040600D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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Barber, J Stanasolovich, D [+details]


This article describes a process for making self-aligned polysilicon contacts which allow for a significant increase in circuit density. This process is compatible with standard CMOS FET processes. Step 1 - Following the formation of the recessed oxide (ROX) regions of a semiconductor wafer 12, a layer of polysilicon 14 is deposited, followed by the growth of a thin oxide layer 16. The polysilicon layer is ion implanted with phosphorus. Step 2 - A layer of titanium 18 is evaporated on the polysilicon in a conformal manner. Step 3 - The polysilicon layer 14 is lithographically defined and dry etched using BCl3, HCl/Cl2, and HCl etch gasses in separate etch steps. The resulting device cross-section is shown in Fig. 1. Step 4 - Referring to Fig.