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Synchronization Processing Elements for Highly Parallel Multiprocessor Systems Disclosure Number: IPCOM000040604D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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So, K [+details]


A technique is described whereby multiprocessor (MP) computer architecture is enhanced through the use of a synchronization processing element (SPE) so as to minimize the synchronization overhead in highly parallel MP computer systems. The SPE provides a method of processing any synchronized events in systems which incorporate multiple central processing units (CPUs). With each CPU having its own cache in a highly parallel processing system, the architecture involved in maintaining the coherence of data sharing among all the caches is most complex and expensive to implement. As a result, it is difficult to cache the synchronization variables and often impossible. Even if the CPU's operate the synchronization variables at the memory level, these variables can be "hot spots" which degrade the overall system performance.