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Parallel Simulated Annealing Method for Highly Parallel Multiple Computer Processors

IP.com Disclosure Number: IPCOM000040608D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue


Related People

Darema-Rogers, F Kirkpatrick, S Norton, VA [+details]


A technique is described whereby simulated annealing (SA) algorithms are executed in parallel format for solving optimization problems, such as the placement of computer chips and wiring for circuit network configurations. Several variant approaches are discussed, utilizing SA as the optimization method and so as to enable multiple computer processors to function cooperatively in the execution of the algorithm in parallel format. In "serial" SA chip placement algorithms, pairs of chips are typically selected randomly and their positions are considered for exchange by computing the effect of the exchange on cost factors, such as the length of wire needed to connect all the chips in the network.