Browse Prior Art Database

Via Interposer for Accommodating Expansion Mismatch

IP.com Disclosure Number: IPCOM000040616D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Shaw, JM Wilczynski, JS Witman, DF [+details]

Abstract

Providing a via interposer, with controlled collapse chip connection vias configured identically to the connection site configuration of two opposing integrated circuits, greatly elongates the solder connection paths and thus permits greater thermomechanical stress without breaking connections. (Image Omitted) Controlled collapse chip connection technologies are widely used for assembling semiconductor chips to substrates. However, as chip and package sizes increase and power requirements increase, the thermal load and expansion mismatches between the components grow. This expansion mismatch stresses the connections and causes them to fail. One method for accommodating expansion mismatch is to stretch the solder column of each connection. Figs. 1-3 show the via interposer which creates the effect of a stretched solder column.