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Marching Test Improvement for RAM Built-In Self Test

IP.com Disclosure Number: IPCOM000040623D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Carval, JL Renard, J [+details]

Abstract

This article describes an original way to entirely apply any Marching Test Algorithm to all the cells of any given RAM independent of the number of data inputs (DIs) and the number of addresses of the product. The Marching Test Algorithm is generally applied only to the RAM addresses, so each N bit word of the RAM (N = number of DI) is considered as an elementary cell for the algorithm. Therefore, any coupling fault between cells of the same RAM word cannot be detected. So the Marching Test Algorithm is not completely applied to the product, and some of the potential electrical faults would not be detected. To improve the test effectiveness, the idea is to consider the RAM DI as address complement. Then, for a RAM with M addresses and N Date inputs, the 2M x N Bit word RAM becomes a N x 2M x 1 bit word RAM.