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MICROPROCESSOR ERROR DETECTION USING a 'CHECKING on STORE' ALGORITHM

IP.com Disclosure Number: IPCOM000040625D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bechdel, JF Mitchell, JA [+details]

Abstract

A method of providing error detection and fault isolation on a general- purpose interface floating point microprocessor which has only minimal on-chip error detection is accomplished through a dual-chip scheme in which one chip checks the other. A modification to the dual-chip scheme has two single-chip floating point processors incorporated into a central electronics complex through the use of an interface adapter chip. The floating point unit (FPU) works as described in the following. The FPU is a three-chip set consisting of an interface adapter and two custom-designed single-chip floating point processor chips. The unit operates as a bus unit on the processor bus and receives all instructions from the instruction processing unit (IPU).