BOOTH ENCODER/SELECTOR COMPARATOR for HIGH SPEED MULTIPLIER
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Today processing requires very high speed multiplication. Arithmetic multiplication is usually realized as conditions of partial product. One of the design constraints is, then, to reduce the number of additions in order to speed up the operation. (Image Omitted) Some techniques, such as the Booth's method, have been previously proposed. The present disclosure shows how this method can be efficiently respected, implemented in CMOS technology in terms of speed and density. The first part of this operation requires encoding 3 bits of the multiplier to generate Booth coefficients. These will be then used by a selector/comparator circuit, as shown in Fig. 1. The Booth coefficients generated are -2, -1, 0, 1, 2.