Browse Prior Art Database

System Bus Adapter for Attaching a General Usage Floating Point Processor

IP.com Disclosure Number: IPCOM000040630D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bechdel, JA Bronson, TC Mitchell, JA [+details]

Abstract

In a system having a microcoded instruction processing unit (IPU) there are several choices for implementing floating point capability. One possibility is to integrate an existing or general usage floating point processor. To do this, the system must either be designed to accommodate the interface of the floating point processor or a separate interfacing mechanism must be provided. A described floating point unit (FPU) system bus adapter provides a means to employ a single bus, general usage floating point processor in an intermediate-sized system having separate busses for commands, operands, and data in addition to a specific control protocol. The adapter works as described in the following. As seen in Fig.