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Multiple Use of Dram Control Inputs to Reduce Testing Time Disclosure Number: IPCOM000040631D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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Related People

Clinton, MP Kilmer, CA Parent, RM Redman, TM Tewarson, DK Thoma, EP [+details]


A memory array which is divided into two halves, AX 10 and AY 20, is shown in the figure. The Data Input/Output for Bit N (DI/O-N) 30 is used to write into AX through X-IN 12 and AX-N 14 or into AY through Y IN 22A and AY-N 24. The array AX is read out through X-OUT 16A to N-OUT 18, an Off Chip Driver (OCD), which drives out through pad DI/O-N 30. Array AY is written into through Y-IN 22A and AY-N 24 and read out through Y-OUT 16B to N-OUT 18 in a similar fashion. A control pin DS/DG-N 40 is used to block storage of Bit N during a normal write cycle to AX or AY through X-IN 12 or Y-IN 22A or to block the read out of Bit N through X-OUT 16A or Y-OUT 16B during a normal read cycle if desired. DS/DG-N thus allows partial storing or output masking of the individual array bits.