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Non-Isotropic PROCESS for Etching Polysilicon With Slope Control

IP.com Disclosure Number: IPCOM000040641D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bergendahl, AS Duncan, BF Hakey, MC Horak, DV [+details]

Abstract

A method for etching intrinsic or implanted polysilicon with suitable slope control in a manufacturing tool operation is disclosed. The technique uses reflowed resist masking along with complete erosion control. The unetched structure shown in Fig. 1 is comprised of reflowed resist 10 over a native oxide 12 on the surface of a 3300- angstrom polysilicon layer 14 which rests on a 150-angstrom triple dielectric gate 16. Following the removal of the exposed native oxide 12 using Process A (Table A), a bias notch 18 (Fig. 2) is created using Process B (Table B). Next, a simultaneous etch of resist 10 and polysilicon 14A (Fig. 2), using Process A, is carried out until the notch 18A (Fig. 3) is within 300 angstroms of the gate 16, as shown in Fig. 3.