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New Approach to Level Sensitive Scan Design Testing

IP.com Disclosure Number: IPCOM000040647D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bula, O Gomez, RS [+details]

Abstract

Level sensitive scan design (LSSD) semiconductor chips equipped with some additional scan path monitoring circuitry will result in a reduction in test data and output pin requirements. A block diagram overview of the design utilized by the new test method is shown in the figure. Circuitry added to an LSSD chip design includes: a) "N" bit shift latches for data compression and a reset circuit. b) "N" bit compare circuit. c) "N" bit parity generator. d) "N" latch multiplexer for data, plus two additional latches, i.e., one for a parity compression bit and one for the comparator result bit. A reset circuit is also needed.