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Single Mask and Imaging for a Dual Level Self Aligned Definition Disclosure Number: IPCOM000040649D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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Cronin, JE [+details]


A novel semiconductor fabrication process sequence is reported to form interlevel metal via interconnections, self aligned to the bottom metal, without a via mask. A problem of chemical vapor deposition (CVD) metals not filling varying size holes is also a useful tool in the fabrication of self aligned metal lines to interlevel via contacts or studs and eliminates a mask step. By designing M1 lines to bloom wherever an interlevel via is required, as shown in Fig. 1 (top view), a self aligned via can be fabricated without an additional mask step. Initially, a first level metal (M1) is defined by utilizing a reactive ion etch (RIE) through a thick mask material, as shown in the cross-section. Next, a CVD oxide is deposited and planarized, as shown in Fig. 2.