Address Key Register Table to Allow Multiple 16-Bit Computer Data And/Or Instruction Address Spaces for Each Level Status Block
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
A technique is described whereby a computer processor, which uses a set of segment register banks to describe the address spaces of the programs being executed, may be extended to allow multiple data and/or instruction address spaces for each single program that is executed. The concept allows programs in either privileged or non-privileged states to use one or more instruction address spaces and one or more data address spaces available for their execution, while maintaining system integrety. Each program execution is represented by a level status block (LSB) and is able to execute with an address key register (AKR) table instead of a single AKR.