Address Key Register Table Extension for 16-Bit Level Status Block Computers
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
A technique is described whereby a table, which outlines an extended form of addressing context information, is added to an existing hardware context information control block of a computer processor. This technique extends and allows optimization of the management of the addressing capabilities of programs to be executed. The address key register (AKR) table is added as an extension to the level status block (LSB) by utilizing an address space key value and address pointer to the AKR table maintained in main storage of the computer. The currently active AKR index numbers and permanent AKR index numbers are kept in the extended LSB to reflect the processor context information required for setting the correct AKR values from the AKR table when resuming a preempted LSB.