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Branching Between Processor Instruction Address Spaces Using Address Key Register Table and Linkage Stack

IP.com Disclosure Number: IPCOM000040674D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bourke, DG Newman, PE Tsevdos, JT [+details]

Abstract

This article describes a technique which provides an efficient open subroutine linkage and return between one or more instruction address spaces, thereby allowing programs larger than 128KB of instructions. Also, an architected linkage stack allows recursive subroutine call and return. In a processor in which each extended level status block (LSB) contains an address space key and an address pointer to a stack control block, the stack control block points to a linkage which is used as a push-down (LIFO) stack for saving and restoring context for subroutine calls and return. Two non-privileged subfunctions of a SFAKT instruction (set AKR from address key table) provide the subroutine linkage and return functions that utilize the linkage stack along with the address key register (AKR) table.