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Optimal Algorithm for Finding Minimal Height Binary Slicing Tree for VLSI Chip Design

IP.com Disclosure Number: IPCOM000040678D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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Luk, WK Tamminen, MI Wong, CK [+details]


A technique is described whereby an algorithm is used to optimize the computational requirements for deriving the maximum height of equivalent binary slicing tree representations, as related to the physical design of VLSI semiconductor chips. The concept is defined for general ordered trees, not only slicing trees, enabling the concept to be utilized in other applications. Physical design of a VLSI chip typically requires slicings be represented as binary trees, whereby the computational aspects of the algorithms involved depend upon the height of the binary slicing tree. Distinct steps are followed, so as to provide requirements of floorplanning, global wiring, detailed wiring and layout of macros.