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Method for Improving Geometric Packaging of Circuit Chip Modules: Utilizing Top-Down Slicing-Based Floorplanning

IP.com Disclosure Number: IPCOM000040679D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
LaPotin, DP [+details]

Abstract

A technique is described whereby the top-down floorplanning approach to geometric packaging of integrated circuit (IC) modules is improved by optimizing the topology while considering the geometry and connectivity of the modules. The approach is particularly well suited to designs which contain a predominance of fixed shaped components, such as datapaths, gate arrays and predefined library modules. Floorplanning can be considered as the assignment of circuit components or modules to a chip image, subject to electrical and physical constraints, and occurs during the early stages of the integrated circuit (IC) design process. A number of floorplanning methods have been derived, such as bottom-up, top-down partitioning and flat approaches.