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Floorplanning Method for Semi-Custom VLSI Chips

IP.com Disclosure Number: IPCOM000040691D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Cagle, JW Masleid, RP Patel, PT Waters, BI [+details]

Abstract

A method of chip floorplanning that is better suited to semi-custom VLSI chips than previous state-of-the-art methods is described. (Image Omitted) Floor planning in VLSI design is necessary in order to achieve smaller chip sizes. Existing state-of-the-art floorplanning tools either assume that all logic blocks are of a constant size and shape, or that all logic macro sizings are to be decided by the floorplanning program. Neither of these cases is true in semi-custom VLSI chips, where the chip consists of both predefined (Dataflow) macros and undefined (Random Logic) macros. Dataflow macros are bit-oriented logic functions that deal with busses of signals, such as a 32-bit register. Since these types of macros can be extremely common, they are physically implemented in advance of chip logic completion.