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Shared Master/Slave Device Disclosure Number: IPCOM000040755D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

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Related People

Duffield, NJ Marquart, DW Morse, RD [+details]


The device includes data flow controller 10 having shared data registers 12, flag 14 and control registers 16 and connected between CPU bus interface 18 and I/O bus interface 20. Bus 18 is connected to CPU 22, and I/O bus 20 is connected to various devices, such as arbitration unit 24, service processor 26 and I/O controllers 28. Arbitration unit 24 may control which device is on bus 20; service processor 26 may debug hardware; and I/O controllers 28 may control a connected disk drive, all of these being for example. When designing a master/slave device (a device which both issues and services requests) to interface to an I/O bus, the master and slave operations must be controlled so that they do not interfere with each other. The simplest way to do this is to provide separate Master and Slave facilities.