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Phase Jitter Reducer

IP.com Disclosure Number: IPCOM000040767D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Haymes, CL [+details]

Abstract

This article describes a phase jitter reducer for dejitterizing signals on a communications network, such as a local area network (LAN). The phase jitter reducer extracts clock signals from the backbone ring of the local area network and uses it for reclocking data onto the ring. Fig. 3 shows a LAN having a backbone ring 10, a plurality of phase jitter reducers and a plurality of wiring closets. (Image Omitted) Referring now to Fig. 1, each phase jitter reducer includes ports A, B, C and D. Port A accepts signals from an input ring segment while port D outputs signals on an output ring segment. Similarly, port D supplies signals into the wiring closet and port C accepts signals from the wiring closets. Each wiring closet includes a plurality of serially connected multi-station access units (MSAUs). Fig.