Multi-Plate Storage Capacitor for DRAM
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
A multiple plate storage capacitor can be constructed for a dynamic random-access memory (DRAM) cell resulting in less sensitivity to soft error effects and having higher speeds. (Image Omitted) A fabrication process for a multi-plate trench capacitor cell in a p-epitaxy, n-well CMOS wafer is shown in Figs. 1-4. Assuming n-well 1 on a p-epitaxy layer 2 of p+ substrate 3, pad oxide 4 is grown and nitride 5 and oxide 6 are deposited, as shown in Fig. 1. Trench capacitor region 7 is patterned and etched to the n-well surface. In Fig. 2, oxide 6 is used as a mask to selectively remove some of the silicon by reactive ion etching (RIE). Polysilicon layer 8 is deposited and selectively etched by RIE to leave sidewalls 9. If necessary, a thin oxide can be grown prior to polysilicon deposition to serve as a stop during etching.