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Thin Film Transistor for Macroelectronic Applications

IP.com Disclosure Number: IPCOM000040796D
Original Publication Date: 1987-Jan-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Greeson, JC Poley, NM [+details]

Abstract

The above drawing and the below-listed sequence of steps describe a method for fabricating thin film transistors to improve tolerance control where the thin film transistors cover a large area, for example, in an active matrix liquid crystal flat panel display. The channel length or source-drain spacing is patterned early in the fabrication cycle. This early patterning permits spacing to be established with a tight tolerance. The patterning is followed by a series of low tolerance fabrication steps. Reference Step Fig. 1 Coat glass substrate 10 with transparent conductor 12. Fig. 2 Form conductor pattern. Fig. 3 Selectively pattern photoresist 14. Fig. 4 Deposit metal layer 16 and N+aSi:H layer 18. Fig. 5 Lift off areas having photoresist. Fig.