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Method to Enhance Flexibility of the Floating Point Accelerator Unit

IP.com Disclosure Number: IPCOM000040934D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Hornung, LM Schwartz, AA Smith, SM Voltin, JA [+details]

Abstract

The purpose of a floating point accelerator is to provide enhanced floating point hardware. This generally consists of interface logic, control logic, and one or more floating point (FPUs). If more than one FPU is used, they may be of the same or different types and may operate in parallel or may do independent operations. Fig. 1 is generalized block diagram of a floating point accelerator.