Browse Prior Art Database

CMOS Memory Sorted for Yield Versus Reliability

IP.com Disclosure Number: IPCOM000041004D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Gray, KS Morrish, JR [+details]

Abstract

A dynamic random access memory (DRAM) chip is designed and equipped to be operated with or without bootstrapped word lines. While the bootstrapped (higher) voltage level on the word lines provides higher output signal and thus high yield, the higher voltage level reduces reliability. Thus, a first sort of those chips which provide acceptable output signal without bootstrapped word lines provides chips for high reliability applications. Word line bootstrapping is enabled on remaining chips by blowing a fuse or changing D.C. voltage level on one pad. Chips thus enabled for word line bootstrapping are then tested for use in applications not requiring the higher reliability.