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Browse Prior Art Database

Tristate Data Compaction for Semiconductor Test Purposes

IP.com Disclosure Number: IPCOM000041106D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bula, O Gomez, RS [+details]

Abstract

The use of on chip binary to trinary data decode circuitry for compacting data will better utilize some VLSI test systems and expand the information content per pin of a device under test.