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The use of on chip binary to trinary data decode circuitry for compacting data will better utilize some VLSI test systems and expand the information content per pin of a device under test.
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Tristate Data Compaction for Semiconductor Test Purposes
The use of on chip binary to trinary data decode circuitry for compacting data
will better utilize some VLSI test systems and expand the information content per
pin of a device under test.
Decode logic is incorporated on chip such that binary data is fed into the
decode logic circuit and trinary date is produced at the output. By converting
binary data to trinary data, a data compaction of approximately 1.5 to 1 is
realized and has the effect of reducing the number of dedicated/shared I/O pins
required for testing.
VLSI testers equipped to recognize trinary data can detect the
a) Binary one (1)
b) Binary zero (0)
c) Trinary (H)
In product usage, the trinary state (high impedance) allows multiple device
pins to be tied together without interfering with one another. For test purposes,
the trinary state can be used to provide expanded data information from a single
pin or group of pins needed to provide pass/fail information. The following chart
compares the I/O pin requirements for binary and trinary information states:
Binary Binary Tristate Trinary
Pins States Pins States
2 4 1 3
3 8 2 9
5 32 3 27
6/7 64/128 4 81
8 256 5 243
9 512 6 729
16 64K 10/11 59K/177K
The use of tristate pins for chip testing allows more information per pin per
test cycle, and by compacting test data, the test operation is made more
productive. For example, assume that two nodes internal to the chip are to be