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Clock Frequency Multiplication by Powers of Two Disclosure Number: IPCOM000041141D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-02

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DasGupta, S [+details]


During the design of a logic system, particularly when existing pieces of logic, designed in different groups, are integrated to build a system, there is a need, sometimes, for a clock frequency that is higher than the available clock frequency. The easy, though not always acceptable, solution is to add a separate oscillator to provide the additional clocks. Unfortunately, the problem is that separate oscillators do not necessarily run together in synchronism, resulting in metastability when signals from one clock system have to be stored in latches controlled by another clock system. Metastability, in turn, requires care in handling and additional hardware to avoid it. The drawing shows a frequency doubler circuit and a way to cascade several of such circuits to produce frequency multiplication by powers of two.