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Register And Operand Conflict Mechanism

IP.com Disclosure Number: IPCOM000041163D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Karne, R [+details]

Abstract

This article describes a mechanism for conflict resolution in a data processing environment which pre-decodes instructions and queues operands for execution. An interlock mechanism is provided to detect when an instruction being decoded is waiting execution in queue. A simpler interlock mechanism is also provided to detect operand address conflicts which are in the store queue and which may be on the way to memory or waiting in the operand queue for execution. A Tag-array mechanism is provided in the address generation logic and also in the execution element to sequence through the operation.