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Random Access Memory Redundancy Via a Programmable Logic Array

IP.com Disclosure Number: IPCOM000041218D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Bula, O Gomez, RS Koch, GS Woyke, JA [+details]

Abstract

A programmable logic array (PLA) is programmed to decode an address input of a random access memory (RAM) chip. When selected, the PLA routes data to and from data input/output (I/O) pins to storage cells which are activated by the decoded line of the PLA.